Over 10 years we help companies reach their financial and branding goals. Engitech is a values-driven technology agency dedicated.

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411 University St, Seattle, USA

engitech@oceanthemes.net

+1 -800-456-478-23

// Join Our Team

Come build the future
with DPI

We believe that solving tomorrow’s challenges requires different types of people, different competencies, different solutions and a different way of thinking. We believe engineers and developers can change the world.

If you’re looking for a fast-paced, action-oriented and fun workplace, we are looking for you!

Current Job Openings

Designation: Physical Design Engineer
Experience: 3-10 Years
Location: Banglore/Hyderabad

Job Description:

• Experience in complete PNR from floorplan, Placement, post placement timing closure, clock tree synthesis, Routing, Post route timing fixing, DRC fixing, PI fixing (IR violation) and closing all required matrices in ECO.
• Good knowledge of TCL, shell and PERL scripting.
• Experience in APR (PNR) and ECO using ICC2 (Synopsys) & INNOVUS (cadence) Tools.
• Experience of working in 4nm,5 nm, 7nm, 10nm, 16nm technology.
• Experience of doing floorplan with complex design and large number of macros.
• Flow setup of synthesis, which include the Timing constraints and logical, physical constraints.

Designation: FPGA Design Engineer
Experience: 2-10 Years
Location: Banglore/Hyderabad

Job Description:

• Experience with FPGA test automation/regression is preferred
• Synthesis, P&R, and timing closure of various design IPs into FPGAs
• Functional and timing verification of FPGA design using simulation
• In-system verification of FPGA design on the system
• Writing verification test benches and automation of test cases
• Regression testing of FPGAs (simulation and in-system)
• Verification of serdes, BER testing, and eye diagram verification

Designation: DFT Engineer
Experience: 2-10 Years
Location: Banglore/Hyderabad

Job Description:

• Design/verification for Clock/JTAG/Analog/DFT IP
• Scan Insertion, ATPG, scan verification, and pattern generation
• Memory BIST insertion, validation, and pattern generation
• Analysis of Functional Design for Testability, including product functionality and access through external connections, BIST and Board Level Diagnostics, control of significant circuits, and isolation of functional blocks for testing
• Create and maintain DFT timing constraints
• SoC DFT architecture specification including test muxing and DfT RTL coding
• IEEE1149.1 Boundary Scan design
• Pattern debug on ATE
• Should have working knowledge and Hands-on experience in any one of the industry-standard tools from Mentor/Synopsys/Cadence

Designation: MS CRM Technical Consultant of D365
Experience: 3+yrs Development, Build and deployment exp, with MS-CRM .net platform
Location: Hyderabad

Job Description:

• Extensive implementation experience in installation, configuration, customization, and extension of Microsoft Dynamics CRM 2015, 2016, and D365 as well as doing the deployment for the applications developed.
• Experience designing and development of Plug-ins and Workflows in CRM to meet business process flow requirements including Sales, Marketing, and Services.
• Having experience on Views, Solutions, exporting and importing a data from and to Excel sheets.
• Developed and customized the dashboards for Sales/marketing in Dynamics CRM.
• Customizing MSCRM 2011, CRM 2013, CRM 2015, CRM 2016 and Dynamics 365
• CRM SDK and exposure to Web services.
• Customizations: Plug-in in .NET to communicate with CRM.
• Experience working on Plug-ins – Plug-in scenario, registering plug-in using a developer tool kit.
• Experience working on Workflows and their process creation.
• Experience working on Ribbon Customizations using third-party Tools.
• Should have good knowledge on out-of-box CRM functionality, customizing, and extending the CRM application.